C-slow retimed parallel histogram architectures for consumer imaging devices. Ĭ-slow retimed parallel histogram architectures for consumer imaging devicesĬadenas, O., Sherratt, R.S., Huerta, P., Wen-Chung, K. IEEE Transactions on Circuits and Systems II: Express Briefs. A parallel quantum histogram architecture. Megson, G.M., Cadenas, O., Sherratt, R.S., Huerta, P. Ī parallel quantum histogram architecture Rapid preconditioning of data for accelerating convex hull computations. Rapid preconditioning of data for accelerating convex hull computations in: 2014 International Conference on Computing, Networking and Communications (ICNC), February 3-6, 2014 in Honolulu, USA. Acceleration and visualization of Dynamic Network Optimization. Internal research group report.Īcceleration and visualization of Dynamic Network Optimization Median Filter Architecture by Accumulative Parallel Counters. Median Filter Architecture by Accumulative Parallel CountersĬadenas, J.O., Megson, G.M. An Empirical Evaluation of Preconditioning Data for Accelerating Convex Hull Computations.

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